Multi-phase clock generators have a wide range of applications in radio-frequency (RF) and mixed-mode (MM) circuits. For example, many RF communications circuits use quadrature amplitude modulation (QAM) for efficient use of the channel bandwidth. A QAM modulator uses an inphase and quadrature phase component of a RF frequency, which are 90 degrees apart in phase, to modulate two stream of base-band data with bandwidth of Δf in a single channel of Δf.
In serial wireline communication circuits, lower frequency multi-phase clocks can be used to serialize or deserialize the low-speed parallel data into a high-speed serial stream of data. FIG. 1 is a diagram that illustrates a multi-phase sampling scheme for serial link communications. As is seen, there is an input data line 12 which is coupled to a plurality of component clock signals ck0-ck4. Each clock 14a-14d is coupled to a respective sampler (16a-16d). Each clock 14a-14d clocks the sampling instant that its respective sampler will use to determine the value of the input data line 12. As is also seen, there are wave forms that represent a set of component clock signals 18a-18d for the multi-phase clock that correspond to clock signals 14a-14d respectively. As is seen, each sampler samples the data from data line 12 on the rising edge. The advantage of using multi-phase clock generators in multi-gigabit serial links is generating an on-chip multi-GHz clock.
However, a major problem that can limit the use of multi-phase clock generation for high-speed data communication or RF communication is the phase offset between the adjacent clock phases, which directly degrades the performance of the system.
FIG. 2 is a block diagram illustrating the same sampling scheme as FIG. 1, except there are phase offsets, for example, as shown, samplers 14a′, 14b′ and 14c′. As is seen, in this diagram only sampler 14d receives the full data signal. This phase offset is caused by a number of sources, including but not limited to, mismatch in different stages of a multi-stage oscillator, the oscillator clock buffers, and periodic ripples on the oscillator or buffers control signal and supply voltage.
In QAM systems, phase offset between inphase and quadrature phases results in interference between the two quadrature RF bands of data. In serial communication, phase offset shows up as a timing error that degrades system performance both in the transmitting and receiving of data. In data transmission using multiple phases, phase error among clock phases causes a data symbols to be longer and a symbol to be shorter than the idea symbol width. The shorter data symbols are harder to be detected by the receiver as they have less timing margin. In the receiver, multiple clock phase error results in timing error in sampling of data that effectively increases system bit error rate (BER) by sampling the data symbol at a non-ideal point.
Other techniques have been adopted in the past to address the phase offset problem in multi-phase clock generators. For example, a technique proposed in C. H. Park, et. al., “A 1.8 GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching,” IEEE JSSC, May 2001, pp. 777-783, has the advantage that it used only one phase detector to correct all phases, by switching the phase detector to measure the difference between a reference signal and multiple phases from a multi-stage oscillator at a time, and apply the output of the phase detector to the corresponding delay adjusting circuit for that phase. The advantage of this scheme is that it does not suffer from mismatches in the phases detector. However, a major drawback of this approach is that the phases from the multi-stage oscillator go through multiple stages of retiming and multiplexing before final correction by the phase detector loop.
As a result, although the phase offset of the clock phases after the retiming and multiplexing stages are zero, the original phase will still experience some phase error due to mismatch in different retiming and multiplexing paths for each phase. In addition, this scheme is much more complex in implementation and the active area used in the scheme is more than an order of magnitude larger than the proposed design in this application.
Another approach as proposed in L. Yu and W. M. Snelgrove entitled “A novel adaptive mismatch cancellation system for quadrature IF radio receivers,” IEEE Trans. Circuits Syst. II, June 1999, pp. 789-801, adds complexity in the clock signal path that limits the performance of the system, is also limited to just few applications, e.g. image rejection in RF systems.
Finally, an approach proposed in B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits Syst. II, June 1997, pp. 428-435, has the advantage of simplicity of design and does not introduce complexity in the clock signal path, however, it does not offer a continuous adjustment during circuit operation. This is a serious drawback for circuits that are sensitive to temperature and voltage variations during operation.
Accordingly, what is needed is a system and method for minimizing phase offset in a communications circuit that overcomes the above-identified problems. The system should be competitive with existing integrated circuits, should be easily implemented and cost effective. The present invention addresses such a need.